Power factor correction at the low-voltage (LV) bus usually starts with a capacitor bank — and for a steady, predictable inductive load it works. But modern plants run variable-frequency drives, UPS rectifiers, and PV inverters whose reactive demand swings minute to minute. On those buses the fixed bank becomes the wrong tool. A static var generator (SVG) is the same job done dynamically. This article quantifies where the two diverge and why it matters for compliance and losses.
Two ways to supply reactive power
A switched capacitor bank is a passive device: its VAR output is fixed by the installed capacitance, switched in discrete steps. It cannot see the bus — it delivers what it is sized for. An SVG is a voltage-source converter (VSC) built on high-frequency IGBTs. It measures the bus continuously and injects or absorbs reactive current in real time across all four quadrants. The control law is essentially i_q* = f(V_bus, PF_setpoint) — it drives local voltage and power factor to the setpoint every few milliseconds.
Response time: sub-cycle vs tens of milliseconds
This is the decisive number. A capacitor bank steps in 10–20 ms and only one direction. An LV SVG responds in under 1 ms and regulates to ±1%, holding PF at 0.99+ even as the load swings. The gap shows up as flicker: when a large motor starts or an arc process dips the bus, the SVG props up voltage before the sag propagates; the bank has barely begun to switch.
Harmonic interaction — the hidden risk
A fixed capacitor's shunt susceptance can resonate with the grid impedance at a harmonic order, amplifying distortion rather than reducing it. IEEE 519 caps LV THDi at ~5% and individual harmonics at ~3%; a mistuned bank pushes you the wrong way. An SVG adds no shunt resonance point and, combined with an active harmonic filter (AHF), actively suppresses harmonics instead of amplifying them.
Power factor regulation: 0.99+ vs a swing
Capacitor banks typically hold PF in the 0.80–0.95 band and overshoot into overvoltage when the load lightens or under-correct when it peaks. Low PF inflates line current: dropping PF from 0.95 to 0.80 raises current ~19%, which increases I²R losses and can force a 10–20% transformer derating. An SVG holds PF near unity continuously, trimming the monthly reactive penalty.
Engineering deployment checklist
1. Measure the reactive profile at the PCC over a full duty cycle.
2. Place the SVG at the load bus feeding the variable-load cluster.
3. Audit existing capacitors for parallel-resonance risk.
4. Check weak-grid margin — size for worst-case voltage dip.
5. Leave headroom (15–25%) for added drives or chargers.
The upgrade path: IGBT → SiC
A conventional LV SVG runs IGBTs capped near 150°C, switching typically under 20 kHz. Migrating the bridge to SiC MOSFETs (200°C junction, ~10× breakdown field, 2–3× switching frequency, ~50% lower switching loss) widens the control bandwidth and shrinks the cabinet for the same kVAr — the direction CHITEK's LV SVG platform is built on.
Bottom line
Where the load is steady, a capacitor bank still earns its place. Where it moves, an SVG is the only compensation fast enough to hold PF at 0.99+ without resonance risk. CHITEK's LV SVG platforms are sized from a real measurement and built around exactly this dynamic, VSC-based approach.
What power factor is your bus actually holding through the day — and how far does it swing between light and peak load?
CHITEK Technical Team
5 min read